The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to a method and structure for a silicon on insulator (SOI) device body contact.
Integrated circuit technology relies on transistors to formulate vast arrays of functional circuits. The complexity of these circuits requires the use of an ever increasing number of linked transistors. As the number of transistors required increases, the surface area that can be dedicated to a single transistor dwindles. It is desirable then, to construct transistors which occupy less surface area on the silicon chip/die.
In one example, integrated circuit technology uses transistors conjunctively with Boolean algebra to create a myriad of digital circuits, also referred to as logic circuits. In a typical arrangement, transistors are combined to switch or alternate an output voltage between just two significant voltage levels, labeled logic 0 and logic 1. In an alternate example, integrated circuit technology similarly uses transistors combined with capacitors to form memory cells. Here, the data is stored in electronic form as a charge on the capacitor. The charge, or absence of charge, on the capacitor translates to either a logic 1 or 0. Most logic systems use positive logic, in which logic 0 is represented by zero volts, or a low voltage, e.g., below 0.5 V; and logic 1 is represented by a higher voltage.
Integrated circuits, including transistors, are typically formed from either bulk silicon starting material, silicon on insulator (SOI) starting material, or SOI material that is formed from a bulk semiconductor starting material during processing. The SOI complementary metal oxide semiconductor (CMOS) technology, however, has been viewed as a likely successor to conventional bulk technology since it provides a prospect of greater circuit performance. This increase in performance results from the lower parasitic junction capacitances and the improved transistor characteristics and tolerances. Basic to the feature of isolating the active silicon layer from the substrate by an intervening insulator layer is the so called xe2x80x9cfloating bodyxe2x80x9d effect on device characteristics. Since the bodies of individual devices are not in direct electrical contact to the conducting substrate, their electrical potential can vary with time depending on leakage currents and parasitic capacitive coupling to other electrodes. Such an effect is clearly undesirable and represents a major stumbling block to the introduction of SOI as a viable product technology.
One approach to handle the uncertain body potential is to include margins within the circuit design to allow for the floating body effect. While this requires no technology action, it diminishes the performance benefits of SOI. Another approach is to minimize the floating body effect by providing an enhanced leakage path to the device body from the device source. This is a partial solution since it merely limits the amount by which the body potential may vary relative to the source and does not allow the voltage to be set at any particular optimum value. Further, it necessarily creates an electrically asymmetric device which limits its acceptability. Other techniques include providing a separate conducting contact to the device bodies. To date, however, the methods proposed have proven cumbersome and come at the price of decreased device density or a compromise in the lower parasitic junction capacitance that motivates the use of SOI.
Thus what is needed is an improved method and structure for implementing SOI transistors, or devices, which provide a predictable electrical potential in the body of the device without sacrificing the benefits attained from using the SOI structure. Any improved method and structure should also conserve surface space on the semiconductor die and maximize device density.
The above mentioned problems with silicon on insulator (SOI) devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A method and structure are provided which accord improved performance for such devices.
In particular, an illustrative embodiment of the present invention includes a silicon on insulator (SOI) device on a substrate. The device includes a single crystalline semiconductor structure which has a first source/drain region, a body region, and a second source/drain region. A gate is formed on a gate oxide which is located above the body region. An insulator layer separates the single crystalline semiconductor structure from the substrate. Further, a body contact is self-aligned with the gate and couples the substrate to a portion of the body region.
In another embodiment, a body contacted transistor on an insulator layer is provided. The transistor includes an active region. The active region has a first source/drain region, a second source/drain region, and a body region. A gate is located above the body region and between the first and second source/drain region. A body contact is coupled to a substrate in an isolation region. The body contact is further coupled to the body region.
In another embodiment, a silicon on insulator (SOI) device is provided. The device includes a substrate. An insulator layer is formed on the substrate. The device includes a planar semiconductor structure which has an upper surface and opposing sidewalls. The planar semiconductor structure also includes a first source/drain region, a body region, a second source/drain region, and a gate. The planar semiconductor structure is formed on the insulator layer. A conductive sidewall member is included in the device. The conductive sidewall member is self-aligned with the gate and couples the substrate to one of opposing sidewalls.
In another embodiment, a method of fabricating a silicon on insulator (SOI) device is provided. The method includes forming a single crystalline semiconductor structure which has an upper surface. The structure is formed to include a first source/drain region, a body region with opposing sidewalls, and a second source/drain region. The structure is formed on an insulator layer on a substrate. A gate is formed on the single crystalline semiconductor structure. The gate is formed such that it extends beyond portions of the single crystalline semiconductor structure to cover portions of an isolation region. A body contact is formed self-aligned with the gate and couples the substrate to one of the opposing sidewalls of the body region.
In another embodiment, a method of forming a body contacted transistor on an insulator layer is provided. The method includes forming an active region of the transistor. The active region is formed to include a first source/drain region, a second source/drain region, and a body region. A gate is formed above the body region and between the first and second source/drain region. A body contact is formed to which couples to a substrate in an isolation region. The body contact is formed such that it additionally couples to the body region.
Thus, a method and structure for an improved silicon on insulator (SOI) device are provided. The method and structure include a body contact that is formed from epitaxial growth from the substrate to the body region of the device. The body contact is self-aligned with the gate in an isolation region of the device and therefore does not increase parasitic capacitance in the device. The structure conserves surface space on the semiconductor die and maximizes device density while preserving the performance benefits of the SOI structure.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.